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0V to 16V, Dual Hot-Swap Controller with 10-Bit
Current and Voltage Monitor and 4 LED Drivers
Table 35. ADC Maximum Voltage Conversion Register Format (Low-Order Bits)
Description:
Maximum voltage conversion result, low-order bits [1:0]
Register Title:
Register Addresses:
max_ch0_mon_lsb
0x0F
max_ch1_mon_lsb
0x13
R
R
R
R
R
R
R/W
R/W
RESET
VALUE
vmax_1
vmax_0
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Using the Voltage and Current
Peak-Detection Registers
The voltage and current minimum- and maximum-value
records in register locations 0x08 through 0x17 can be
reset by writing a 1 to the appropriate location in register
peak_log_rst (see Table 36). The minimum-value regis-
ters are reset to 0x3FF, and the maximum-value registers
are reset to 0x00.
As long as a bit in peak_log_rst is 1, the corresponding
peak-detection registers are disabled and are cleared
to their power-up reset values. The voltage and current
minimum- and maximum-detection register contents
for each signal can be held by setting bits in register
peak_log_hold (see Table 37). Writing a 1 to a location
in peak_log_hold locks the register contents for the cor-
responding signal and stops the min/max detection and
logging; writing a 0 enables the detection and logging.
Note that the peak-detection registers cannot be cleared
while they are held by register peak_log_hold.
The combination of these two control registers allows the
user to monitor voltage and current peak-to-peak values
during a particular time period.
Table 36. Peak-Detection Reset-Control Register Format
Description:
Register Title:
Register Address:
Reset control bits for peak-detection registers
peak_log_rst
0x41
R
—
bit 7
R
—
bit 6
R
—
bit 5
R
—
bit 4
R/W
Ch1_v_rst
bit 3
R/W
Ch1_i_rst
bit 2
R/W
Ch0_v_rst
bit 1
R/W
Ch0_i_rst
bit 0
RESET
VALUE
0x00
Table 37. Peak-Detection Hold-Control Register Format
Description:
Register Title:
Register Address:
Hold control bits for peak-detection registers; per signal
peak_log_hold
0x42
R
—
bit 7
R
—
bit 6
R
—
bit 5
R
—
bit 4
R/W
Ch1_v_hld
bit 3
R/W
Ch1_i_hld
bit 2
R/W
Ch0_v_hld
bit 1
R/W
Ch0_i_hld
bit 0
RESET
VALUE
0x00
______________________________________________________________________________________
29
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